This relates to an integrated circuit semiconductor device having a plurality of adjacent photodiodes and to a method of manufacturing the same.
Photodiodes generate current upon receiving light. They are widely used as light-receiving elements for optical pick-up devices incorporated into optical disc devices, such as CD or DVD devices. A photodiode is constituted by a pn junction formed in a semiconductor material. A reverse bias is applied to the pn junction to widen the depletion layer, and a high electric field is applied. Electron-hole pairs are generated in the depletion layer by the absorbed light. Under the attraction of the electric field, electrons move to the n-type semiconductor region, while holes move to the p-type semiconductor region, thereby causing a current to flow.
Types of photodiodes include PIN photodiodes and avalanche photodiodes. PIN photodiodes include a p- or n-layer or other intrinsic layer (referred to as Layer I) having a conductivity impurity at low concentration between p and n layers and can easily widen the depletion layer at a low voltage. Avalanche photodiodes include a region where avalanche decay occurs.
Japanese Kokai Patent Application No. 2001-320079 discloses a method of manufacturing a photodiode that can be used to remove an insulation film on the top layer of the diode without having film peel-off or leakage. An example photodiode formed by this method is shown in FIGS. 26A and 26B.
As shown in FIGS. 26A and 26B, a p−-type epitaxial layer 101 is formed as Layer I on a p++-type silicon semiconductor substrate 100, and an n-type epitaxial layer 102 is formed on the layer 101 to form a pn junction. An n+-type semiconductor region 103 is formed in a surface portion of n-type epitaxial layer 102 in the PIN photodiode region. A silicon nitride layer 103a is formed on the surface in the central part of n+-type semiconductor region 103. Silicide layer 103b, made of platinum silicide, etc., is formed near the edge of n+-type semiconductor region 103 in the outer periphery of silicon nitride layer 103a. Silicon nitride layer 103a and silicide layer 103b have a film thickness of, for example, 30 nm. An insulating film 104 is formed using a LOCOS process to surround the PIN photodiode region.
A ring-shaped mask layer 105 made of metal is formed from n+-type semiconductor region 103 in the outer periphery of the PIN photodiode to element-separating insulation film 104, and an interlayer insulating film 106 is formed on the mask layer 105. An opening H is formed in interlayer insulation film 106 along the inner periphery of metal layer 105 to expose the surface of silicon nitride layer 103a and silicide layer 103b on n+-type semiconductor region 103 in the photodiode region. A surface protective layer 108 is formed to cover the opening H.
For the PIN photodiode PD formed with the described configuration, when a reverse bias is applied to n+-type semiconductor region 103 and p−-type epitaxial layer 101, the depletion layer is widened from the pn junction surface. When light is incident on the formed depletion layer, electron hole pairs are generated, and signals are generated. In this case, mask layer 105 is connected to n+ semiconductor region 103, and voltage can be applied to n+-type semiconductor region 103 via mask layer 105.
As shown in FIGS. 27A and 27B, a method of forming the described PIN photodiode PD includes forming p-type epitaxial layer 101 and n-type epitaxial layer 102 on p++-type silicon semiconductor substrate 100, and performing element isolation using LOCOS (local oxidation of silicon) element-separating insulation film 104. The n+-type semiconductor region 103 is formed by implanting ions into a surface part of n-type epitaxial layer 102 in the PIN photodiode region separated by LOCOS element-separating insulation film 104, etc. A silicon nitride layer 103a with a thickness of about 30 nm is formed on the surface in the central part of n+-type semiconductor region 103. With silicon nitride layer 103a used as a siliciding mask, a silicide layer 103b, made of platinum silicide, etc., and having a thickness of about 30 nm is formed on the surface near the edge of n+-type semiconductor region 103 in the outer periphery of silicon nitride layer 103a. Then, a metal layer, made of TiW, etc., is deposited in a thickness of 200-300 nm by means of sputtering, followed by patterning to form mask layer 105 that covers n+-type semiconductor region 103 and is extended all the way to LOCOS element-separating insulation film 104. Then, insulation film 106 is formed on the entire surface of mask layer 105. In this case, insulation film 106 is formed by laminating a plurality of layers by depositing silicon oxide by CVD (chemical vapor deposition) with TEOS (tetraethyl orthosilicate) used as the raw material, or by depositing a BPSG (borophosphosilicate glass) film, or by depositing silicon nitride via CVD.
Then, as shown in FIGS. 28A and 28B, a resist film 107 with a pattern that opens the photosensitive region of the photodiode is formed on insulation film 106. After that, dry etching, such as RIE (reactive ion etching), is performed to remove the insulation film 106 from the photosensitive region and form opening H with the mask layer 105 serving as an etch stop layer. Then, as shown in FIGS. 29A and B, the portion of mask layer 105 exposed in the opening H is removed selectively with respect to n+-type semiconductor region 103 (silicon substrate) and insulation film 106 by means of wet etching to expose the n+-type semiconductor region 103. Then, a surface protective layer 108 is formed on the entire surface to obtain the semiconductor device having the PIN photodiode PD as shown in FIGS. 26A and 26B.
In the method of manufacturing a semiconductor device having such a PIN photodiode, when removing the insulation film 106 from the diode, since mask layer 105 serves as an etch stop, even if dry etching is used so that no hollow parts are formed on the inner wall surface of opening H to cause film peeling, no damage will be caused that will allow leakage because the silicon substrate is protected by mask layer 105 in that step. Also, when removing the portion of mask layer 105 exposed in the opening H, even if wet etching is used to avoid damage to the silicon substrate, mask layer 105 can be removed selectively without forming hollow parts on the inner wall surface of opening H of insulation film 106.
However, when such a photodiode is used as a light-receiving element for an optical pick-up device incorporated into a CD, DVD, or other optical disc device, in order to obtain the tracking error signal or focus error signal from the signal fed back from the optical disc, it is necessary to use a photodiode integrated circuit (PDIC) formed by combining a plurality of photodiodes.
FIG. 30 is a plan view of a PDIC formed by combining, for example, four PIN photodiodes. This figure shows how a laser spot S, which is the signal fed back from the optical disc, is incident on the four PIN photodiodes PD1-4. In this case, laser spot S is incident to target the center of the four PIN photodiodes PD1-4. However, since the part in the intervals between the four PIN photodiodes PD1-4 becomes a dead area, it is desirable to reduce the intervals between the four PIN photodiodes PD1-4 to, for example, 5 μm or less in order to increase the sensitivity.
FIG. 31 is a plan view illustrating the light-receiving surfaces of the photodiodes when the method described in Japanese Kokai Patent Application No. 2001-320079 is applied to the four PIN photodiodes PD1-4 with the intervals reduced to about 5 μm as mentioned. The four PIN photodiodes PD1-4 are covered by a common mask layer 110. After the opening is formed in the insulation film, the mask layer exposed in the opening is removed. In this case, however, mask layer 110, which is a common conductive layer, is connected to the n+-type semiconductor region equivalent to the light-receiving surface of each of the four PIN photodiodes PD1-4. As a result, a short circuit between the diodes becomes a problem.
FIG. 32 is a plan view illustrating the light-receiving surface of a photodiode in the case when the mask layers are formed independently, and the four PIN photodiodes PD1-4 with an opening formed in each of them are laid out as close to each other as possible. Here, independent mask layers (111-114) are formed with respect to the four PIN photodiodes PD1-4, respectively. In this layout, however, the intervals between the four PIN photodiodes PD1-4 are increased to 20 μm, making it difficult to use them as the light-receiving element of an optical pick-up device.